Invention Grant
- Patent Title: Reduction of silicon area for ethernet PFC protocol implementation in queue based network processors
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Application No.: US14811900Application Date: 2015-07-29
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Publication No.: US09912604B2Publication Date: 2018-03-06
- Inventor: Roman Nos , Noam Efrati , Sagi Gurfinkel
- Applicant: Freescale Semiconductor Inc.
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- Main IPC: H04L12/863
- IPC: H04L12/863 ; H04L12/721 ; H04L29/12

Abstract:
In a pipelined network processor, a first stage in the pipeline is responsive to receipt of a pause indication from a third stage. The pause indication is associated with one of a plurality of ports and priority classes of frames advancing through the pipeline. The first stage asserts a hold indication to a second stage in response to the pause indication. The second stage is responsive to the hold indication by marking frames associated with the one of a plurality of ports and priority classes as they arrive from the pipeline at the second stage by returning them to the first stage interface instead of transmitting them to the third stage. The marked frames are stored in memory external to the network processor.
Public/Granted literature
- US20170034069A1 Reduction Of Silicon Area for Ethernet PFC Protocol Implementation In Queue Based Network Processors Public/Granted day:2017-02-02
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