Invention Grant
- Patent Title: Techniques and devices for performing arithmetic
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Application No.: US15025770Application Date: 2014-10-02
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Publication No.: US09916131B2Publication Date: 2018-03-13
- Inventor: Eugene George Walters, III
- Applicant: The Penn State Research Foundation
- Applicant Address: US PA University Park
- Assignee: The Penn State Research Foundation
- Current Assignee: The Penn State Research Foundation
- Current Assignee Address: US PA University Park
- Agency: Dinsmore & Shohl LLP
- International Application: PCT/US2014/058803 WO 20141002
- International Announcement: WO2015/051105 WO 20150409
- Main IPC: G06F7/501
- IPC: G06F7/501 ; G06F7/505 ; G06F7/575
Abstract:
A two-operand adder circuit is provided. The two-operand adder circuit may be configured to receive a bit of a second addend, a carry-in bit, and one or more bits encoding a bit of a first addend, and to provide an output representing a sum of the bit of the first addend, the bit of the second addend, and the carry-in bit.
Public/Granted literature
- US20160246571A1 TECHNIQUES AND DEVICES FOR PERFORMING ARITHMETIC Public/Granted day:2016-08-25
Information query
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