A method, system, and computer program product perform distributed timing analysis of an integrated circuit design. Aspects include dividing the integrated circuit design into non-overlapping design partitions, each design partition including nodes and edges, each edge interconnecting a pair of the nodes. Aspects also include identifying speculative nodes among the nodes, each speculative node having at least one and less than all timing inputs available and being associated with a speculative processing task, and identifying non-speculative nodes among the nodes, each non-speculative node having all timing inputs available and being associated with a non-speculative processing task. Assigning each of the non-speculative processing tasks to a respective processor of a processing system specific to each design partition for timing analysis processing is done prior to assigning any of the speculative processing tasks.