Invention Grant
- Patent Title: Automatic generation of test layouts for testing a design rule checking tool
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Application No.: US14779351Application Date: 2013-04-01
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Publication No.: US09916412B2Publication Date: 2018-03-13
- Inventor: Mikhail Anatolievich Sotnikov , Alexander Leonidovich Kerre
- Applicant: Mikhail Anatolievich Sotnikov , Alexander Leonidovich Kerre
- Applicant Address: US TX Austin
- Assignee: NXP USA, Inc.
- Current Assignee: NXP USA, Inc.
- Current Assignee Address: US TX Austin
- International Application: PCT/RU2013/000272 WO 20130401
- International Announcement: WO2014/163519 WO 20141009
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F11/36

Abstract:
A method of automatically generating a set of test layouts for testing a design rule checking tool is described. A layout is a point in a space of several coordinates, and the design rule comprises N design constraints numbered 1 to N, wherein N is greater or equal two and each design constraint is a boolean-valued function of one or more of the coordinates. The set of test layouts includes: one or more zero-error layouts; one or more one-error layouts; and one or more two-error layouts. A zero-error layout is a layout that satisfies all of the design constraints. A one-error layout is a layout that violates exactly one of the design constraints. A two-error layout is a layout that violates exactly two of the design constraints.
Public/Granted literature
- US20160048629A1 AUTOMATIC GENERATION OF TEST LAYOUTS FOR TESTING A DESIGN RULE CHECKING TOOL Public/Granted day:2016-02-18
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