Invention Grant
- Patent Title: Self-aligned source and drain regions for semiconductor devices
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Application No.: US15483273Application Date: 2017-04-10
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Publication No.: US09916984B2Publication Date: 2018-03-13
- Inventor: Joel P. de Souza , Bahman Hekmatshoartabari , Jeehwan Kim , Siegfried L. Maurer , Devendra K. Sadana
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Tutunjian & Bitetto, P.C.
- Agent Louis J. Percello
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/092 ; H01L29/78 ; H01L21/283 ; H01L21/3213 ; H01L29/08 ; H01L29/40 ; H01L29/66 ; A23C9/123 ; A23C11/08 ; A23C9/13
Abstract:
A method for forming a semiconductor device includes patterning a gate conductor, formed on a substrate, and a two-dimensional material formed on the gate conductor. Recesses are formed adjacent to the gate conductor in the substrate, and a doped layer is deposited in the recesses and over a top of the two-dimensional material. Tape is adhered to the doped layer on top of the two-dimensional material. The tape is removed to exfoliate the doped layer from the top of the two-dimensional material to form source and drain regions in the recesses.
Public/Granted literature
- US20170213736A1 SELF-ALIGNED SOURCE AND DRAIN REGIONS FOR SEMICONDUCTOR DEVICES Public/Granted day:2017-07-27
Information query
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