Invention Grant
- Patent Title: Semiconductor device having contacts in drawing area and the contacts connected to word lines extending from element formation area
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Application No.: US15226852Application Date: 2016-08-02
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Publication No.: US09917049B2Publication Date: 2018-03-13
- Inventor: Fumiharu Nakajima , Toshiya Kotani , Hiromitsu Mashita , Takafumi Taguchi , Ryota Aburada , Chikaaki Kodama
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Tokyo
- Assignee: Toshiba Memory Corporation
- Current Assignee: Toshiba Memory Corporation
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2011-066181 20110324
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/033 ; H01L21/311 ; H01L21/3213 ; H01L27/06 ; H01L27/11524 ; H01L27/11551 ; H01L27/1157 ; H01L27/11578 ; H01L21/768

Abstract:
According to one embodiment, a semiconductor device includes interconnects extending from a element formation area to the drawing area, and connected with semiconductor elements in the element formation area and connected with contacts in the drawing area. The interconnects are formed based on a pattern of a (n+1)th second sidewall film matching a pattern of a nth (where n is an integer of 1 or more) first sidewall film on a lateral surface of a sacrificial layer. A first dimension matching an interconnect width of the interconnects and an interconnects interval in the element formation area is (k1/2n)×(λ/NA) or less when an exposure wavelength of an exposure device is λ, a numerical aperture of a lens of the exposure device is NA and a process parameter is k1. A second dimension matching an interconnect interval in the drawing area is greater than the first dimension.
Public/Granted literature
- US20160343658A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2016-11-24
Information query
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