Invention Grant
- Patent Title: Method of manufacturing an integrated stacked package with a fan-out redistribution layer (RDL) and a same encapsulating process
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Application No.: US15130211Application Date: 2016-04-15
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Publication No.: US09917072B2Publication Date: 2018-03-13
- Inventor: Chen-Hua Yu , Kuo-Chung Yee , Hao-Yi Tsai , Tin-Hao Kuo
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L25/065 ; H01L21/768 ; H01L25/00 ; H01L21/3105 ; H01L23/48 ; H01L23/528 ; H01L23/00 ; H01L23/367 ; H01L23/31

Abstract:
A method includes forming a first through-via from a first conductive pad of a first device die, and forming a second through-via from a second conductive pad of a second device die. The first and second conductive pads are at top surfaces of the first and the second device dies, respectively. The first and the second conductive pads may be used as seed layers. The second device die is adhered to the top surface of the first device die. The method further includes encapsulating the first and the second device dies and the first and the second through-vias in an encapsulating material, with the first and the second device dies and the first and the second through-vias encapsulated in a same encapsulating process. The encapsulating material is planarized to reveal the first and the second through-vias. Redistribution lines are formed to electrically couple to the first and the second through-vias.
Public/Granted literature
- US20170084576A1 Integrated Fan-out Stacked SiP and the Methods of Manufacturing Public/Granted day:2017-03-23
Information query
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