Invention Grant
- Patent Title: Memory cell structure for improving erase speed
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Application No.: US14713462Application Date: 2015-05-15
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Publication No.: US09917165B2Publication Date: 2018-03-13
- Inventor: Chang-Ming Wu , Shih-Chang Liu
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L29/788
- IPC: H01L29/788 ; H01L29/792 ; H01L29/423 ; H01L29/66 ; H01L21/28 ; H01L27/11524 ; H01L21/8239

Abstract:
A split-gate flash memory cell for improved erase speed is provided. An erase gate and a floating gate are laterally spaced over a semiconductor substrate. The floating gate has a height increasing towards the erase gate, a concave sidewall surface neighboring the erase gate, and a tip defined an interface of the concave sidewall surface and an upper surface of the floating gate. A control gate and a sidewall spacer are arranged over the upper surface of the floating gate. The control gate is laterally offset from the tip of the floating gate, and the sidewall spacer is laterally arranged between the control gate and the tip. A method for manufacturing the split-gate flash memory cell is also provided.
Public/Granted literature
- US20160336415A1 MEMORY CELL STRUCTURE FOR IMPROVING ERASE SPEED Public/Granted day:2016-11-17
Information query
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