Invention Grant
- Patent Title: Structure and method for transistors with line end extension
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Application No.: US15137501Application Date: 2016-04-25
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Publication No.: US09917192B2Publication Date: 2018-03-13
- Inventor: Shao-Ming Yu , Chang-Yun Chang , Chih-Hao Chang , Hsin-Chih Chen , Kai-Tai Chang , Ming-Feng Shieh , Kuei-Liang Lu , Yi-Tang Lin
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Haynes and Boone, LLP
- Main IPC: H01L21/8238
- IPC: H01L21/8238 ; H01L29/06 ; H01L29/08 ; H01L29/16 ; H01L29/161 ; H01L29/165 ; H01L29/66 ; H01L29/78 ; H01L29/417

Abstract:
A method includes forming an isolation feature in a semiconductor substrate; forming a first fin-like active region and a second fin-like active region in the semiconductor substrate and interposed by the isolation feature; forming a dummy gate stack on the isolation feature, wherein the dummy gate extends to the first fin-like active region from one side and to the second fin-like active region from another side.
Public/Granted literature
- US20160240675A1 STRUCTURE AND METHOD FOR TRANSISTORS WITH LINE END EXTENSION Public/Granted day:2016-08-18
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