Invention Grant
- Patent Title: Multi-die interface for semiconductor testing and method of manufacturing same
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Application No.: US14938835Application Date: 2015-11-11
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Publication No.: US09933479B2Publication Date: 2018-04-03
- Inventor: Hai Dau , Lim Hooi Weng , Kothandan Shanmugam , Christine Bui
- Applicant: Spire Manufacturing, Inc.
- Applicant Address: US CA Fremont
- Assignee: Spire Manufacturing
- Current Assignee: Spire Manufacturing
- Current Assignee Address: US CA Fremont
- Agent Mark Gonzales
- Main IPC: G01R31/28
- IPC: G01R31/28 ; G01R1/067

Abstract:
The present invention includes an interface apparatus for semiconductor testing. The interface apparatus comprises a housing substrate and two product substrates. The first product substrate has a first micro-scale conductive pattern and is situated within a first opening of the housing substrate. The second product substrate has a second micro-scale conductive pattern and is situated within a second opening of the housing substrate. The first and the second micro-scale conductive patterns are aligned to a conductive semiconductor wafer pattern using a continuous translucent media having targets corresponding to the conductive semiconductor wafer pattern.
Public/Granted literature
- US20170131348A1 Multi-die Interface for Semiconductor Testing and Method of Manufacturing Same Public/Granted day:2017-05-11
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