Invention Grant
- Patent Title: Management of core power state transition in a microprocessor
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Application No.: US14833335Application Date: 2015-08-24
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Publication No.: US09933836B2Publication Date: 2018-04-03
- Inventor: Malcolm S. Allen-Ware , Charles R. Lefurgy , Karthick Rajamani , Todd J. Rosedahl , Guillermo J. Silva , Gregory S. Still , Victor Zyuban
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
- Current Assignee Address: US NY Armonk
- Agency: Patterson + Sheridan, LLP
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
A method for adjusting a frequency of a processor is disclosed herein. In one embodiment, the method includes inhibiting one or more processor cores from exiting an idle state. The method further includes determining a number of processor cores requesting exit from the idle state and a number of non-idle processor cores. The method also includes selecting a maximum frequency for the inhibited and non-idle processor cores based on the number of inhibited processor cores requesting exit from the idle state and the number of non-idle processor cores. The method includes setting the maximum frequency for both the inhibited and the non-idle processor cores, and then uninhibiting the processor cores requesting exit from the idle state.
Public/Granted literature
- US20170031418A1 MANAGEMENT OF CORE POWER STATE TRANSITION IN A MICROPROCESSOR Public/Granted day:2017-02-02
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