A memory device includes a non-volatile memory (NVM) array and a memory controller. The NVM array has four partitions in which each partition has as plurality of groups of NVM cells. The memory controller that performs a written operation on each of the four partitions in four cycles per group of NVM cells beginning a clock cycle apart in which two of the four clock cycles for the write operation are for an array write that requires a relatively high current and that the array write for each partition overlaps no more than one other array write so that a peak current of all four write operations is no more than twice the peak current of one group. The NVM cells may be magnetic tunnel junctions (MTJs) which have significantly faster written times than typical NVM cells.