Invention Grant
- Patent Title: Methods and apparatuses for performing multiplication
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Application No.: US15424929Application Date: 2017-02-06
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Publication No.: US09933998B2Publication Date: 2018-04-03
- Inventor: Kuo-Tseng Tseng , Parkson Wong
- Applicant: Kuo-Tseng Tseng , Parkson Wong
- Applicant Address: US CA San Jose US CA Los Altos
- Assignee: Kuo-Tseng Tseng,Parkson Wong
- Current Assignee: Kuo-Tseng Tseng,Parkson Wong
- Current Assignee Address: US CA San Jose US CA Los Altos
- Main IPC: G06F7/487
- IPC: G06F7/487 ; G06F7/483 ; G06F7/53 ; G06F7/48 ; H03K19/20

Abstract:
In a novel computation device, a plurality of partial product generators is communicatively coupled to a binary number multiplier. The binary number is partitioned in the computation device into non-overlapping subsets of binary bits and each subset is coupled to one of the plurality of partial product generators. Each partial product generator, upon receiving a subset of binary bits representing a number, generates a multiplication product of the number and a predetermined constant. The multiplication products from all partial product generators are summed to generate the final product between the predetermined constant and the binary number. The partial product generators are constructed by logic gates and wires connected the logic gates including a AND gate. The partial product generators are free of memory elements.
Public/Granted literature
- US20170168775A1 Methods and Apparatuses for Performing Multiplication Public/Granted day:2017-06-15
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