Embodiments disclose techniques for executing a test case to test a processor by bypassing an instruction pipeline of the processor. In one embodiment, the processor receives a plurality of test cases to execute on the processor. Each test case includes one or more instructions. Once received, the processor loads a plurality of registers with one or more first register values for the test case by bypassing the instruction pipeline. Once loaded, the processor runs the test case using the one or more first register values. The processor then retrieves, from the plurality of registers, one or more second register values associated with results of the test case run, by bypassing the instruction pipeline.