Invention Grant
- Patent Title: Memory system storing 4-bit data in each memory cell and method of controlling thereof including soft bit information
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Application No.: US15238087Application Date: 2016-08-16
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Publication No.: US09934847B2Publication Date: 2018-04-03
- Inventor: Kenji Sakurada , Masanobu Shirakawa
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G11C11/56
- IPC: G11C11/56 ; G11C16/08 ; G11C29/42
Abstract:
According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE, UPPER, and HIGHER pages from a NAND memory 100 that includes QLCs each being capable of retaining a 4-bit value. An ECC circuit 260 of a memory controller 200 decodes the acquired HB information and SB1 to SB4 information on the four pages.
Public/Granted literature
- US20170263312A1 MEMORY SYSTEM AND METHOD OF CONTROLLING THEREOF Public/Granted day:2017-09-14
Information query
