Invention Grant
- Patent Title: Slit stress modulation in semiconductor substrates
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Application No.: US15056620Application Date: 2016-02-29
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Publication No.: US09935000B2Publication Date: 2018-04-03
- Inventor: James Mathew , Yunjun Ho , Zhiqiang Xie , Hyun Sik Kim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Hanley, Flight & Zimmerman, LLC
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L21/762 ; H01L21/02 ; H01L25/00 ; H01L25/065 ; H01L27/115 ; H01L21/66

Abstract:
A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor substrate. The semiconductor substrate includes a slit between adjacent stacked transistor layers. The first material coats walls of the slit to reduce a first width of the slit between the adjacent stacked transistor layers to a second width. A second process is controlled to apply a second material to the semiconductor substrate. The second material is to be deposited in the second width of the slit. The first material and the second material are to form a solid structure in the slit between the adjacent stacked transistor layers.
Public/Granted literature
- US20170250108A1 SLIT STRESS MODULATION IN SEMICONDUCTOR SUBSTRATES Public/Granted day:2017-08-31
Information query
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