Invention Grant
- Patent Title: Fin spacer protected source and drain regions in FinFETs
-
Application No.: US14851535Application Date: 2015-09-11
-
Publication No.: US09935011B2Publication Date: 2018-04-03
- Inventor: Kuo-Cheng Ching , Ting-Hung Hsu , Chao-Hsiung Wang , Chi-Wen Liu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/8234 ; H01L27/088 ; H01L29/165 ; H01L21/8238 ; H01L21/84 ; H01L29/66 ; H01L29/78 ; H01L27/092 ; H01L27/12 ; H01L21/02 ; H01L21/306 ; H01L21/311 ; H01L21/762

Abstract:
A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
Public/Granted literature
- US20160005656A1 Fin Spacer Protected Source and Drain Regions in FinFETs Public/Granted day:2016-01-07
Information query
IPC分类: