Invention Grant
- Patent Title: Methods for manufacturing semiconductor device and for detecting end point of dry etching
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Application No.: US15630385Application Date: 2017-06-22
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Publication No.: US09935023B2Publication Date: 2018-04-03
- Inventor: Toshikazu Hanawa , Kazuhide Fukaya , Kentaro Yamada
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Koutou-ku, Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Koutou-ku, Tokyo
- Agency: Sughrue Mion, PLLC
- Priority: JP2015-167575 20150827
- Main IPC: G01L21/30
- IPC: G01L21/30 ; G01R31/00 ; H01L21/66 ; H01L21/311 ; H01L21/768 ; H01L23/522 ; H01L23/532 ; G01N21/73 ; G01N21/84 ; G01N21/68 ; H01J37/32
Abstract:
A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer insulating film, the emission intensities of at least CO, CN, and AlF are monitored such that an end point of the dry etching of the interlayer insulating film is detected based on the emission intensities thereof.
Public/Granted literature
- US20170287794A1 METHODS FOR MANUFACTURING SEMICONDUCTOR DEVICE AND FOR DETECTING END POINT OF DRY ETCHING Public/Granted day:2017-10-05
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