Invention Grant
- Patent Title: Reducing solder pad topology differences by planarization
-
Application No.: US14392345Application Date: 2014-06-05
-
Publication No.: US09935069B2Publication Date: 2018-04-03
- Inventor: Jipu Lei , Stefano Schiaffino , Alexander H. Nickel , Mooi Guan Ng , Salman Akram
- Applicant: Lumileds LLC
- Applicant Address: US CA San Jose
- Assignee: LUMILEDS LLC
- Current Assignee: LUMILEDS LLC
- Current Assignee Address: US CA San Jose
- Agency: Volpe and Koenig, P.C.
- International Application: PCT/IB2014/061968 WO 20140605
- International Announcement: WO2014/207590 WO 20141231
- Main IPC: H01L23/00
- IPC: H01L23/00 ; B23K1/20 ; H01L21/48 ; H01L23/498

Abstract:
A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a substrate. The chip is provided with solder pads that may have different heights. A dielectric layer is formed between the solder pads. A relatively thick metal layer is plated over the solder pads. The metal layer is planarized to cause the top surfaces of the metal layer portions over the solder pads to be in the same plane and above the dielectric layer. A substantially uniformly thin layer of solder is deposited over the planarized metal layer portions so that the top surfaces of the solder bumps are substantially in the same plane. The chip is then positioned over a substrate having corresponding metal pads, and the solder is reflowed or ultrasonically bonded to the substrate pads.
Public/Granted literature
- US20160181216A1 REDUCING SOLDER PAD TOPOLOGY DIFFERENCES BY PLANARIZATION Public/Granted day:2016-06-23
Information query
IPC分类: