Invention Grant
- Patent Title: Method for inducing strain in vertical semiconductor columns
-
Application No.: US15164441Application Date: 2016-05-25
-
Publication No.: US09935198B2Publication Date: 2018-04-03
- Inventor: Jean-Pierre Colinge , Gwan Sin Chang , Carlos H. Diaz
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L29/78
- IPC: H01L29/78 ; H01L29/06 ; H01L21/02 ; H01L21/768 ; H01L23/535 ; H01L29/423 ; H01L29/66 ; H01L29/786

Abstract:
A vertical Metal-Oxide-Semiconductor (MOS) transistor includes a substrate and a nano-wire over the substrate. The nano-wire comprises a semiconductor material. An oxide ring extends from an outer sidewall of the nano-wire into the nano-wire, with a center portion of the nano-wire encircled by the oxide ring. The vertical MOS transistor further includes a gate dielectric encircling a portion of the nano-wire, a gate electrode encircling the gate dielectric, a first source/drain region underlying the gate electrode, and a second source/drain region overlying the gate electrode. The second source/drain region extends into the center portion of the nano-wire. Localized oxidation produces a local swelling in the structure that generates a tensile or compressive strain in the nano-wire.
Public/Granted literature
- US20160268427A1 Method for Inducing Strain in Vertical Semiconductor Columns Public/Granted day:2016-09-15
Information query
IPC分类: