Invention Grant
- Patent Title: Semiconductor device
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Application No.: US14967024Application Date: 2015-12-11
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Publication No.: US09935620B2Publication Date: 2018-04-03
- Inventor: Naoshi Ishikawa
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee: RENESAS ELECTRONICS CORPORATION
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2015-054649 20150318
- Main IPC: H03K5/15
- IPC: H03K5/15

Abstract:
The present invention provides a technique for further improving the processing efficiency in accordance with the setting of the number of waits in a semiconductor device that arbitrates data transfer through a bus between a plurality of bus masters and a plurality of bus slaves. A semiconductor device includes a clock supplying unit that independently supplies clocks to a plurality of bus slaves and a plurality of bus masters. The number of waits in accordance with an operating frequency can be set for each bus slave such as a memory. As the setting of the number of waits becomes smaller, the clock supplying unit improves the operating frequency by controlling a phase difference between the clocks supplied to the bus masters and the bus slaves in accordance with the number of waits set for each bus slave.
Public/Granted literature
- US20160277013A1 SEMICONDUCTOR DEVICE Public/Granted day:2016-09-22
Information query
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