Invention Grant
- Patent Title: Interconnect topology with staggered vias for interconnecting differential signal traces on different layers of a substrate
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Application No.: US14570791Application Date: 2014-12-15
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Publication No.: US09936570B2Publication Date: 2018-04-03
- Inventor: Min Wang , Russell N. Shryock
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: H05K1/02
- IPC: H05K1/02 ; H01P3/02 ; H05K1/11

Abstract:
An interconnect topology is disclosed that includes a plurality of interconnections, each of which is coupled together using a via, where at least two of the vias are staggered with respect to each other. In one embodiment, the interconnect topology comprises a substrate, multiple signal traces routed through the substrate on multiple layers, and a plurality of vias, where each via couples a pair of the signal traces to form an interconnection between different ones of the multiple layers, and where a pair of vias comprise a first via to carry a positive differential signal via and a second via to carry a negative differential signal that are coupled to signal traces to form a differential signal pair. The differential first and second vias are staggered with respect to each other.
Public/Granted literature
- US20160172734A1 DIFFERENTIAL INTERCONNECT TOPOLOGY IN A SUBSTRATE WITH STAGGERED VIAS Public/Granted day:2016-06-16
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