Invention Grant
- Patent Title: Implementing hardware accelerator for storage write cache management for reads with partial read hits from storage write cache
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Application No.: US14939762Application Date: 2015-11-12
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Publication No.: US09940252B2Publication Date: 2018-04-10
- Inventor: Brian E. Bakke , Joseph R. Edwards , Robert E. Galbraith , Adrian C. Gerhard , Daniel F. Moertl , Gowrisankar Radhakrishnan , Rick A. Weckwerth
- Applicant: International Business Machines Corporation
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Joan Pennington
- Main IPC: G06F12/0895
- IPC: G06F12/0895 ; G06F12/122 ; G06F12/0868 ; G06F12/0891 ; G06F12/0893 ; G06F13/40 ; G06F13/42 ; G06F13/28
Abstract:
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides are provided. The controller includes a hardware write cache engine implementing hardware acceleration for storage write cache management. The hardware write cache engine performs reads with partial read hits from storage write cache with no firmware involvement for greatly enhancing performance.
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