According to one embodiment, an interface of a memory system includes a circuit configured to adjust output resistance for data output. When the circuit has received a command in a second state, the circuit adjusts output resistance during a first period. The first period is a period from when the interface completes reception of the command to when the interface starts transmission of data read from the memory. The second state is a state in which power consumption is lower than that in a first state in which operation is caused by a command.