Invention Grant
- Patent Title: Internal clock signal control for display device, display driver and display device system
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Application No.: US15078217Application Date: 2016-03-23
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Publication No.: US09940869B2Publication Date: 2018-04-10
- Inventor: Keiji Nose
- Applicant: Synaptics Japan GK
- Applicant Address: JP Tokyo
- Assignee: Synaptics Japan GK
- Current Assignee: Synaptics Japan GK
- Current Assignee Address: JP Tokyo
- Agency: Patterson + Sheridan, LLP
- Priority: JP2015-073751 20150331
- Main IPC: G09G3/20
- IPC: G09G3/20 ; G09G5/00 ; H04N21/43 ; H04L7/00 ; G06F3/038

Abstract:
A display device includes a display panel and a display driver driving the display panel. The display driver is connected to a host with a clock lane and at least one a data lane. The display driver includes: an interface circuit configured to receive an external clock signal from the host via the clock lane, receive a data signal from the host via the data lane, and output reception data transmitted over the data signal; a control circuit configured to output an internal clock signal synchronous with the external clock signal; and a drive circuitry configured to drive the display panel in response to image data included in the reception data in synchronization with the internal clock signal fed from the control circuit. The control circuit is configured to feed the internal clock signal in response to a type of a reception packet included in the reception data.
Public/Granted literature
- US20160293096A1 INTERNAL CLOCK SIGNAL CONTROL FOR DISPLAY DEVICE, DISPLAY DRIVER AND DISPLAY DEVICE SYSTEM Public/Granted day:2016-10-06
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