Invention Grant
- Patent Title: Write assist circuit for lowering a memory supply voltage and coupling a memory bit line
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Application No.: US15135133Application Date: 2016-04-21
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Publication No.: US09940994B2Publication Date: 2018-04-10
- Inventor: Yifei Zhang , Mark J. Winter
- Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.
- Applicant Address: SG Singapore
- Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Foley & Lardner LLP
- Main IPC: G11C11/00
- IPC: G11C11/00 ; G11C11/419 ; G11C5/14 ; G11C11/412

Abstract:
A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply voltage signal to a voltage supply node of the memory cell using a capacitor. The lower supply voltage signal is lower in voltage level than a supply voltage signal. The method further includes lowering a common signal provided to a write driver using the capacitor.
Public/Granted literature
- US20170294223A1 WRITE ASSIST CIRCUIT FOR LOWERING A MEMEORY SUPPLY VOLTAGE AND COUPLING A MEMORY BIT LINE Public/Granted day:2017-10-12
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