Invention Grant
- Patent Title: Fully depleted silicon-on-insulator (FDSOI) transistor device and self-aligned active area in FDSOI bulk exposed regions
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Application No.: US15388772Application Date: 2016-12-22
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Publication No.: US09941301B1Publication Date: 2018-04-10
- Inventor: David Pritchard , Lixia Lei , Deniz E. Civay , Scott D. Luning , Neha Nayyar
- Applicant: GLOBALFOUNDRIES Inc.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Ditthavong & Steiner, P.C.
- Main IPC: H01L21/8234
- IPC: H01L21/8234 ; H01L27/12 ; H01L29/49 ; H01L21/84 ; H01L29/06 ; H01L29/40 ; H01L29/417 ; H01L29/78

Abstract:
Methods for eliminating the distance between a BULEX and SOI and the resulting devices are disclosed. Embodiments include providing a silicon layer on a BOX layer on a silicon substrate; forming two active areas in the silicon layer, separated by a space; forming first and second polysilicon gates over one active area, a third polysilicon gate over the space, and fourth and fifth polysilicon gates over the other active area, the second and fourth gates abutting edges of the space; forming spacers at opposite sides of each gate; removing the second, third, and fourth gates and the corresponding spacers; removing the silicon layer and BOX layer in the space, forming a trench and exposing the silicon substrate; forming second spacers on sidewalls of the trench; forming raised source/drain regions on each active area; and forming a p-well contact on the silicon substrate between the second spacers.
Information query
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