Invention Grant
- Patent Title: Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methods
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Application No.: US15154276Application Date: 2016-05-13
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Publication No.: US09941359B2Publication Date: 2018-04-10
- Inventor: Robert J. Mears , Hideki Takeuchi
- Applicant: Atomera, Incorporated
- Applicant Address: US CA Los Gatos
- Assignee: ATOMERA INCORPORATED
- Current Assignee: ATOMERA INCORPORATED
- Current Assignee Address: US CA Los Gatos
- Agency: Allen, Dyer, Doppelt + Gilchrist, P.A.
- Main IPC: H01L29/15
- IPC: H01L29/15 ; H01L27/092 ; H01L29/06 ; H01L21/8238 ; H01L29/66 ; H01L29/423 ; H01L21/8234 ; H01L29/78 ; H01L29/10 ; H01L27/088
Abstract:
A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.
Public/Granted literature
Information query
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