Invention Grant
- Patent Title: Semiconductor structure and method
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Application No.: US13525041Application Date: 2012-06-15
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Publication No.: US09945048B2Publication Date: 2018-04-17
- Inventor: Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
- Applicant: Sen-Hong Syue , Pu-Fang Chen , Shiang-Bau Wang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: C30B15/04
- IPC: C30B15/04 ; H01L21/02 ; C30B15/20 ; C30B31/02 ; C30B31/04 ; H01L21/311 ; C30B15/22 ; H01L29/36 ; H01L21/762 ; C30B31/16 ; H01L21/3105 ; C30B29/06 ; H01L21/322 ; C30B15/00 ; C30B33/00 ; H01L29/78
Abstract:
A system and method for providing support to semiconductor wafer is provided. An embodiment comprises introducing a vacancy enhancing material during the formation of a semiconductor ingot prior to the semiconductor wafer being separated from the semiconductor ingot. The vacancy enhancing material forms vacancies at a high density within the semiconductor ingot, and the vacancies form bulk micro defects within the semiconductor wafer during high temperature processes such as annealing. These bulk micro defects help to provide support and strengthen the semiconductor wafer during subsequent processing and helps to reduce or eliminate a fingerprint overlay that may otherwise occur.
Public/Granted literature
- US20130337631A1 Semiconductor Structure and Method Public/Granted day:2013-12-19
Information query
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