- Patent Title: Testing of semiconductor devices and devices, and designs thereof
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Application No.: US15162679Application Date: 2016-05-24
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Publication No.: US09945899B2Publication Date: 2018-04-17
- Inventor: Michael Roehner , Stefano Aresu
- Applicant: Infineon Technologies AG
- Applicant Address: DE Neubiberg
- Assignee: Infineon Technologies AG
- Current Assignee: Infineon Technologies AG
- Current Assignee Address: DE Neubiberg
- Agency: Slater Matsil, LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G01R31/26 ; G01R19/00 ; H01L21/66 ; H01L23/498 ; G01R31/12 ; G01R31/28 ; H01L23/522 ; H01L23/552 ; H01L23/00 ; H01L21/027 ; H01L21/288 ; H01L21/768 ; H01L23/528 ; H01L23/532 ; H01L23/538

Abstract:
In accordance with an embodiment of the present invention, a method of testing a plurality of semiconductor devices includes applying a stress voltage having a peak voltage on a shield line disposed over a substrate. The substrate has functional circuitry of a semiconductor device. A fixed voltage is applied to a first metal line disposed above the substrate adjacent the shield line. The first metal line is coupled to the functional circuitry and is configured to be coupled to a high voltage node during operation. The peak voltage is greater than a maximum fixed voltage. The shield line separates the first metal line from an adjacent second metal line configured to be coupled to a low voltage node during operation. The method further includes measuring a current through the shield line in response to the stress voltage, determining the current through the shield line of the semiconductor device, and based on the determination, identifying the semiconductor device as passing the test.
Public/Granted literature
- US20160266197A1 Testing of Semiconductor Devices and Devices, and Designs Thereof Public/Granted day:2016-09-15
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