Invention Grant
- Patent Title: Semiconductor device manufacturing method
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Application No.: US15151152Application Date: 2016-05-10
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Publication No.: US09945903B2Publication Date: 2018-04-17
- Inventor: Toshitsugu Ishii , Naohiro Makihira , Hidekazu Iwasaki , Jun Matsuhashi
- Applicant: Renesas Electronics Corporation
- Applicant Address: JP Tokyo
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Tokyo
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2015-146314 20150724
- Main IPC: H01L21/66
- IPC: H01L21/66 ; G01R31/28 ; H01L21/56 ; H01L21/67 ; H01L23/495 ; H01L23/00 ; H01L23/31 ; H01L23/544

Abstract:
This invention enhances reliability of an electrical test. A semiconductor device manufacturing method in which a potential (first potential) is supplied by bringing a plurality of first and second test terminals into contact with a plurality of leads, respectively in the step of supplying the potential to the leads (first leads) to carry out the electrical test. The first test terminals come into contact with the leads, individually, and the second test terminals come into contact with the leads in one batch.
Public/Granted literature
- US20170025318A1 SEMICONDUCTOR DEVICE MANUFACTURING METHOD Public/Granted day:2017-01-26
Information query
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