Fetch Less Instruction Processing (FLIP) Computer Architecture for Central Processing Units (CPU). This embodiment relates to computing systems, and more particularly to central processing units in computing systems. The principal object of this embodiment is to provide a Fetch Less Instruction Processing (FLIP) computer architecture using FLIP elements as building blocks for computer program processing. Another object of the embodiment is to use a protocol to interconnect FLIP elements, which makes the current operating systems, program execution models, compilers, libraries and so on to be easily transitioned to the FLIP computer architecture with minimal changes.