Invention Grant
- Patent Title: Method of forming spacers for a gate of a transistor
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Application No.: US15627713Application Date: 2017-06-20
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Publication No.: US09947541B2Publication Date: 2018-04-17
- Inventor: Olivier Pollet , Maxime Garcia-Barros , Nicolas Posseme
- Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Applicant Address: FR Paris
- Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
- Current Assignee Address: FR Paris
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: FR1655739 20160620
- Main IPC: H01L21/28
- IPC: H01L21/28 ; H01L21/3115 ; H01L21/311 ; H01L21/762 ; H01L21/265 ; H01L29/78 ; H01L29/66 ; H01L29/06 ; H01L29/08 ; H01L21/266
Abstract:
A method for forming spacers of a gate of a field effect transistor is provided, the gate including sides and a top and being located above a layer of a semiconductor material, the method including a step of forming a dielectric layer that covers the gate; after the step of forming the dielectric layer, at least one step of modifying the dielectric layer by ion implantation while retaining non-modified portions of the dielectric layer covering sides of the gate and being at least non-modified over their entire thickness; the ions having a hydrogen base and/or a helium base; at least one step of removing the modified dielectric layer using a selective etching of the dielectric layer, wherein the removing includes a wet etching with a base of a solution including hydrofluoric acid diluted to x % by weight, with x≤0.2, and having a pH less than or equal to 1.5.
Public/Granted literature
- US20180012766A1 METHOD OF FORMING SPACERS FOR A GATE OF A TRANSISTOR Public/Granted day:2018-01-11
Information query
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