Invention Grant
- Patent Title: Package with solder regions aligned to recesses
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Application No.: US15417942Application Date: 2017-01-27
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Publication No.: US09947630B2Publication Date: 2018-04-17
- Inventor: Ching-Jung Yang , Hsien-Wei Chen , Hsien-Ming Tu , Chang-Pin Huang , Yu-Chia Lai , Tung-Liang Shao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater Matsil, LLP
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/48 ; H01L23/52 ; H01L23/00

Abstract:
A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
Public/Granted literature
- US20170141054A1 Package with Solder Regions Aligned to Recesses Public/Granted day:2017-05-18
Information query
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