Invention Grant
- Patent Title: Adjusting of patterns in design layout for optical proximity correction
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Application No.: US15239072Application Date: 2016-08-17
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Publication No.: US09952500B2Publication Date: 2018-04-24
- Inventor: Sudeep Mandal , Arun S. Mampazhy
- Applicant: GLOBALFOUNDRIES INC.
- Applicant Address: KY Grand Cayman
- Assignee: GLOBALFOUNDRIES INC.
- Current Assignee: GLOBALFOUNDRIES INC.
- Current Assignee Address: KY Grand Cayman
- Agency: Hoffman Warnick LLC
- Agent Yuanmin Cai
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G03F1/36

Abstract:
Embodiments of the present disclosure include methods, program products, and systems for adjusting an integrated circuit (IC) layout for optical proximity correction (OPC). Methods according to the disclosure can include: defining a target region of the IC design layout, the target region having a plurality of patterns including a first pattern positioned adjacent to a second pattern, wherein an OPC modeling rule of the IC design layout prohibits the first pattern from being adjusted, and wherein the second pattern does not reduce a printability metric of the first pattern; adjusting the design of the second pattern to reduce at least one printing error in the first pattern, wherein a functionality of the second pattern in the IC design layout is unchanged after the adjusting; and implementing OPC on the IC design layout including the target region with the adjusted second pattern therein.
Public/Granted literature
- US20180052388A1 ADJUSTING OF PATTERNS IN DESIGN LAYOUT FOR OPTICAL PROXIMITY CORRECTION Public/Granted day:2018-02-22
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