Invention Grant
- Patent Title: Multicore processor system having an error analysis function
-
Application No.: US14783251Application Date: 2013-04-09
-
Publication No.: US09952954B2Publication Date: 2018-04-24
- Inventor: Rene Graf
- Applicant: SIEMENS AKTIENGESELLSCHAFT
- Applicant Address: DE München
- Assignee: SIEMENS AKTIENGESELLSCHAFT
- Current Assignee: SIEMENS AKTIENGESELLSCHAFT
- Current Assignee Address: DE München
- Agency: Henry M. Feiereisen, LLC
- International Application: PCT/EP2013/057382 WO 20130409
- International Announcement: WO2014/166526 WO 20141016
- Main IPC: G06F11/00
- IPC: G06F11/00 ; G06F11/263 ; G06F11/36 ; G06F11/22

Abstract:
A method for operating a multi-core processor system, wherein different of a program are each executed simultaneously by a different respective processor core of the multi-core processor system includes inserting a breakpoint in a first of the threads for interrupting the first processor core and instead executing an exception handling routine. At least one processor core to be additionally interrupted is determined with the exception handling routine on the basis of an association matrix, and an inter-processor interrupt (IPI) is sent to the at least one processor core by the exception handling routine in order to interrupt the at least one processor core.
Public/Granted literature
- US20160062863A1 MULTICORE PROCESSOR SYSTEM HAVING AN ERROR ANALYSIS FUNCTION Public/Granted day:2016-03-03
Information query