Invention Grant
- Patent Title: Active matrix substrate and display panel
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Application No.: US15316185Application Date: 2015-06-05
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Publication No.: US09953605B2Publication Date: 2018-04-24
- Inventor: Takayuki Nishiyama , Kohhei Tanaka
- Applicant: Sharp Kabushiki Kaisha
- Applicant Address: JP Sakai
- Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee: SHARP KABUSHIKI KAISHA
- Current Assignee Address: JP Sakai
- Agency: Keating & Bennett, LLP
- Priority: JP2014-118048 20140606
- International Application: PCT/JP2015/066395 WO 20150605
- International Announcement: WO2015/186832 WO 20151210
- Main IPC: G09G3/36
- IPC: G09G3/36 ; G02F1/1362 ; G02F1/1345 ; G02F1/1368

Abstract:
Provided is an active matrix substrate that includes a gate line group, a source line group, a pixel electrode arranged in a display area, and a gate line driving circuit (11) formed in the display area. The gate line driving circuit (11) includes an accumulation line that accumulates a voltage for controlling the voltage level of the gate line; an output unit (U1) that controls the voltage level of the gate line according to the voltage of the accumulation line; an accumulated voltage supply unit (U2) that varies the voltage of the accumulation line according to a signal input from another gate line; and accumulated voltage adjustment units (U3) that change the voltage of the accumulation line to a predetermined level according to the control signal. The output unit (U1), the accumulated voltage supply unit (U2), and, the accumulated voltage adjustment units (U3) are arrayed along the gate line, and the output unit (U1) is arranged at a position interposed between the accumulated voltage adjustment units (U3).
Public/Granted literature
- US20170154596A1 ACTIVE MATRIX SUBSTRATE AND DISPLAY PANEL Public/Granted day:2017-06-01
Information query
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