Invention Grant
- Patent Title: Methods of operating memory under erase conditions
-
Application No.: US15638718Application Date: 2017-06-30
-
Publication No.: US09953711B2Publication Date: 2018-04-24
- Inventor: Toru Tanzawa
- Applicant: MICRON TECHNOLOGY, INC.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dicke, Billig & Czaja, PLLC
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C16/14 ; G11C16/04

Abstract:
Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for a memory cell of a string of series-connected memory cells, wherein the first semiconductor material is electrically connected to a second semiconductor material of the first conductivity type through a first conductive material of a second conductivity type different than the first conductivity type, and wherein the second semiconductor material forms a channel region for a different memory cell of the string of series-connected memory cells; and applying a second voltage level, less than the first voltage level, to a control gate of the memory cell and applying a third voltage level, less than the second voltage level, to a control gate of the different memory cell while applying the first voltage level to the first semiconductor material.
Public/Granted literature
- US20170345506A1 METHODS OF OPERATING MEMORY UNDER ERASE CONDITIONS Public/Granted day:2017-11-30
Information query