Invention Grant
- Patent Title: Structure and method of fabricating three-dimensional (3D) metal-insulator-metal (MIM) capacitor and resistor in semi-additive plating metal wiring
-
Application No.: US15288594Application Date: 2016-10-07
-
Publication No.: US09954051B2Publication Date: 2018-04-24
- Inventor: Guan Huei See , Chin Hock Toh , Glen T. Mori , Arvind Sundarrajan
- Applicant: Guan Huei See , Chin Hock Toh , Glen T. Mori , Arvind Sundarrajan
- Applicant Address: US CA Santa Clara
- Assignee: APPLIED MATERIALS, INC.
- Current Assignee: APPLIED MATERIALS, INC.
- Current Assignee Address: US CA Santa Clara
- Agency: Moser Taboada
- Agent Alan Taboada
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L21/02 ; H01L23/522 ; H01L23/532 ; H01L49/02 ; H01L21/311 ; H01L21/3213
Abstract:
Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.
Public/Granted literature
Information query
IPC分类:
