Invention Grant
- Patent Title: Method for manufacturing a semiconductor device having a super junction MOSFET
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Application No.: US15627434Application Date: 2017-06-19
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Publication No.: US09954078B2Publication Date: 2018-04-24
- Inventor: Takahiro Tamura , Yasuhiko Onishi
- Applicant: FUJI ELECTRIC CO., LTD.
- Applicant Address: JP Kawasaki-Shi, Kanagawa
- Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee: FUJI ELECTRIC CO., LTD.
- Current Assignee Address: JP Kawasaki-Shi, Kanagawa
- Agency: Rabin & Berdo, P.C.
- Priority: JP2013-192789 20130918
- Main IPC: H01L21/265
- IPC: H01L21/265 ; H01L29/66 ; H01L29/06

Abstract:
A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n− region with a lower impurity concentration than the n-type drift region.
Public/Granted literature
- US20170294521A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A SUPER JUNCTION MOSFET Public/Granted day:2017-10-12
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