Invention Grant
- Patent Title: Removal of sampling clock jitter induced in an output signal of an analog-to-digital converter
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Application No.: US15603713Application Date: 2017-05-24
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Publication No.: US09954546B2Publication Date: 2018-04-24
- Inventor: Bernd Laquai
- Applicant: Advantest Corporation
- Applicant Address: JP Tokyo
- Assignee: ADVANTEST CORPORATION
- Current Assignee: ADVANTEST CORPORATION
- Current Assignee Address: JP Tokyo
- Main IPC: H03M1/08
- IPC: H03M1/08 ; H03M1/10

Abstract:
An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.
Public/Granted literature
- US20170257107A1 REMOVAL OF SAMPLING CLOCK JITTER INDUCED IN AN OUTPUT SIGNAL OF AN ANALOG-TO-DIGITAL CONVERTER Public/Granted day:2017-09-07
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