Invention Grant
- Patent Title: Memory system and method of controlling cache memory
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Application No.: US14840601Application Date: 2015-08-31
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Publication No.: US09959206B2Publication Date: 2018-05-01
- Inventor: Naoya Fukuchi
- Applicant: Toshiba Memory Corporation
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F12/0802 ; G06F3/06

Abstract:
According to one embodiment, a memory system includes first and second memories, and a controller configured to switch between first and second modes, search whether data of a logical address associated with a read command is stored in the first memory in the first mode, and read the data from the second memory without searching whether the data of the logical address associated with the read command is stored in the first memory in the second mode.
Public/Granted literature
- US20160342511A1 MEMORY SYSTEM AND METHOD OF CONTROLLING CACHE MEMORY Public/Granted day:2016-11-24
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