Invention Grant
- Patent Title: Methods for etching a metal layer to form an interconnection structure for semiconductor applications
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Application No.: US14243677Application Date: 2014-04-02
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Publication No.: US09960052B2Publication Date: 2018-05-01
- Inventor: Sumit Agarwal , Ann Chien , Chiu-Pien Kuo , Mark Hoinkis , Bradley J. Howard
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/3213
- IPC: H01L21/3213 ; H01J37/32 ; H01L21/768

Abstract:
Embodiments of the present invention provide methods for patterning a metal layer, such as a copper layer, to form an interconnection structure in semiconductor devices. In one embodiment, a method of patterning a metal layer on a substrate includes (a) supplying an etching gas mixture comprising a hydro-carbon gas into a processing chamber having a substrate disposed therein, the substrate having a metal layer disposed thereon, (b) exposing the metal layer to an ashing gas mixture comprising a hydrogen containing gas to the substrate, and (c) repeatedly performing steps (a) and (b) until desired features are formed in the metal layer. During the patterning process, the substrate temperature may be controlled at greater than 50 degrees Celsius.
Public/Granted literature
- US20150287634A1 METHODS FOR ETCHING A METAL LAYER TO FORM AN INTERCONNECTION STRUCTURE FOR SEMICONDUCTOR APPILCATIONS Public/Granted day:2015-10-08
Information query
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