Invention Grant
- Patent Title: Passive within via
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Application No.: US13897202Application Date: 2013-05-17
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Publication No.: US09960079B2Publication Date: 2018-05-01
- Inventor: Todd B. Myers , Nicholas R. Watts , Eric C. Palmer , Jui Min Lim
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L21/20
- IPC: H01L21/20 ; H01L21/768 ; H01L21/48 ; H01L23/64 ; H01L23/66 ; H05K1/11 ; H05K1/16 ; H01L23/48 ; H01L23/498 ; H05K3/06 ; H05K3/40 ; H05K3/42
Abstract:
A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.
Public/Granted literature
- US20130249112A1 PASSIVE WITHIN VIA Public/Granted day:2013-09-26
Information query
IPC分类:
