Invention Grant
- Patent Title: Method and structure for wafer level packaging with large contact area
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Application No.: US15287261Application Date: 2016-10-06
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Publication No.: US09960119B2Publication Date: 2018-05-01
- Inventor: Yan Xun Xue
- Applicant: Alpha and Omega Semiconductor Incorporated
- Applicant Address: US CA Sunnyvale
- Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
- Current Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
- Current Assignee Address: US CA Sunnyvale
- Agent Chen-Chi Lin
- Main IPC: H01L23/535
- IPC: H01L23/535 ; H01L21/768 ; H01L21/78 ; H01L23/498 ; H01L21/48 ; H01L23/31 ; H01L23/00 ; H01L23/48 ; H01L21/304 ; H01L21/56 ; H01L25/00

Abstract:
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.
Public/Granted literature
- US20170025356A1 METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA Public/Granted day:2017-01-26
Information query
IPC分类: