- Patent Title: Method of forming body contact layouts for semiconductor structures
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Application No.: US15353617Application Date: 2016-11-16
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Publication No.: US09960236B2Publication Date: 2018-05-01
- Inventor: Dev Alok Girdhar , Jeffrey Michael Johnston
- Applicant: INTERSIL AMERICAS LLC
- Applicant Address: US CA Milpitas
- Assignee: INTERSIL AMERICAS LLC
- Current Assignee: INTERSIL AMERICAS LLC
- Current Assignee Address: US CA Milpitas
- Agency: Foley & Lardner LLP
- Agent Mark J. Danielson
- Main IPC: H01L29/10
- IPC: H01L29/10 ; H01L27/088 ; H01L23/535 ; H01L29/66 ; H01L29/78 ; H01L29/06 ; H01L29/08 ; H01L23/522 ; H01L23/528

Abstract:
Methods for forming body contact layouts for semiconductor structures are disclosed. In at least one exemplary embodiment, a method comprises: forming a plurality of gates disposed on a semiconductor layer, each gate extending parallel to a y-axis in a coordinate space; a source region disposed between two of the plurality of gates; a plurality of body contacts disposed in each source region; and wherein a portion of each body contact, adjacent to the gate, has a width extending parallel to the y-axis that is less than the width of the body contact parallel to the y-axis at a distance on an x-axis from the gate.
Public/Granted literature
- US20170069719A1 BODY CONTACT LAYOUTS FOR SEMICONDUCTOR STRUCTURES Public/Granted day:2017-03-09
Information query
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