A cryptographic processing device includes a processor that generates a first encrypted polynomial, a receiver that receives cryptographic information representing a fourth encrypted polynomial, and cryptographic information representing a second random number, the fourth encrypted polynomial including a first operation result that is a result of an operation of a fifth vector and a sixth vector, the first operation result being obtained by a second encrypted polynomial and a third encrypted polynomial, wherein the second encrypted polynomial is obtained based on the first encrypted polynomial, the second random number, and a second polynomial that corresponds to a third vector obtained by adding zero to the second vector, and the third encrypted polynomial is obtained based on the fifth vector obtained by adding zero to a fourth vector. The processor generates a second operation result that is a result of an operation of the second vector and the fourth vector.