Invention Grant
- Patent Title: Apparatus and method for flushing dirty cache lines based on cache activity levels
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Application No.: US15264548Application Date: 2016-09-13
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Publication No.: US09965023B2Publication Date: 2018-05-08
- Inventor: David Keppel , Kelvin Kwan , Jawad Nasrullah
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson de vos Webster & Elliott LLP
- Main IPC: G06F12/08
- IPC: G06F12/08 ; G06F1/32 ; G06F12/121 ; G06F12/0804 ; G06F12/0891 ; G06F12/0897 ; G06F12/122

Abstract:
A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.
Public/Granted literature
- US20170003734A1 APPARATUS AND METHOD FOR REDUCED CORE ENTRY INTO A POWER STATE HAVING A POWERED DOWN CORE CACHE Public/Granted day:2017-01-05
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