Invention Grant
- Patent Title: Instruction and logic for processor trace information for control flow integrity
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Application No.: US14866254Application Date: 2015-09-25
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Publication No.: US09965280B2Publication Date: 2018-05-08
- Inventor: Michael F. Spear , Gilles A. Pokam
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Alliance IP, LLC
- Main IPC: G06F9/38
- IPC: G06F9/38 ; G06F9/30

Abstract:
A processor includes a front end to decode an instruction and pass the instruction to execution units with branch suffix information. The processor further includes execution units to execute the instruction and a retirement unit to retire the instruction. The instruction is to specify an operation to be conditionally executed based upon a branch suffix to identify previous execution. The processor further includes logic to, upon retirement of the instruction, determine the result of a series of branch operations preceding execution of the instruction, compare the result to the branch suffix information, allow execution and retirement of the instruction based on a determination that the result matches the branch suffix information, and generate a fault based on a determination that the result does not match the branch suffix information.
Public/Granted literature
- US20170090926A1 Instruction and Logic for Processor Trace Information for Control Flow Integrity Public/Granted day:2017-03-30
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