Invention Grant
- Patent Title: Cache storing data fetched by address calculating load instruction with label used as associated name for consuming instruction to refer
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Application No.: US15357943Application Date: 2016-11-21
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Publication No.: US09965281B2Publication Date: 2018-05-08
- Inventor: Mohammad A. Abdallah
- Applicant: Intel Corporation
- Applicant Address: unknown Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: unknown Santa Clara
- Agency: Nicholson De Vos Webster & Elliott, LLP
- Main IPC: G06F9/30
- IPC: G06F9/30
Abstract:
A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instruction formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.
Public/Granted literature
Information query
